Semiconductor memories can experience high failure rates due to “soft” errors (i.e., errors where data in a memory array change prior to or during a given memory access and whose original value can be restored upon rewriting of the data). Causes of soft errors include primarily ionizing radiation effects induced by neutron and alpha particle bombardment and to a much lesser extent due to loss of cell charge, electronic noise, stray radiation, and poor connections. Conventional solutions to reduce the failure rate of semiconductor memories due to soft errors include (i) error control coding (ECC), (ii) materials selection, and (iii) changes to process, bit-cell design and/or circuit design. ECC can include conventional single error correcting and double error detecting (SEC-DED) code implementations.
However, conventional solutions have failed to eliminate semiconductor memory soft errors. Furthermore, existing SEC-DED code implementations are not optimized for (i) minimum circuit area and logic gate count, and/or (ii) maximum performance and reliability.
It would be desirable to have a method and/or architecture for error control coding in semiconductor memory that (i) reduces soft errors, (ii) minimizes circuit area, (iii) optimizes logic gate count, (iv) increases performance, and/or (v) increases reliability.